The total of 145 full papers included in these proceedings were carefully reviewed and selected from 403 submissions. They cover the many dimensions of parallel algorithms and architectures including fundamental theoretical approaches, practical experimental projects, and commercial components and systems.

This book constitutes the refereed proceedings of the 22nd International Conference on Algorithms and Architectures for Parallel Processing, ICA3PP 2022, which was held in October 2022. Due to COVID-19 pandemic the conference was held virtually.

This book constitutes the proceedings of the 22st International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation, SAMOS 2021, which took place in July 2022 in Samos, Greece. The 11 full papers and 7 short papers presented in this volume were carefully reviewed and selected from 45 submissions. The conference covers a wide range of embedded systems design aspects, including machine learning accelerators, and power management and programmable dataflow systems.

This book examines the issue of design of fully integrated frequency synthesizers suitable for system-on-a-chip (SOC) processors. This book takes a more global design perspective in jointly examining the design space at the circuit level as well as at the architectural level. The coverage of the book is comprehensive and includes summary chapters on circuit theory as well as feedback control theory relevant to the operation of phase locked loops (PLLs). On the circuit level, the discussion includes low-voltage analog design in deep submicron digital CMOS processes, effects of supply noise, substrate noise, as well device noise. On the architectural level, the discussion includes PLL analysis using continuous-time as well as discre- time models, linear and nonlinear effects of PLL performance, and detailed analysis of locking behavior. The material then develops into detailed circuit and architectural analysis of specific clock generation blocks. This includes circuits and architectures of PLLs with high power supply noise immunity and digital PLL architectures where the loop filter is digitized. Methods of generating low-spurious sampling clocks for discrete-time analog blocks are then examined.

There has been continuing interest in the improvement of the speed of Digital Signal processing. The use of Residue Number Systems for the design of DSP systems has been extensively researched in literature. Szabo and Tanaka have popularized this approach through their book published in 1967. Subsequently, Jenkins and Leon have rekindled the interest of researchers in this area in 1978, from which time there have been several efforts to use RNS in practical system implementation. An IEEE Press book has been published in 1986 which was a collection of Papers. It is very interesting to note that in the recent past since 1988, the research activity has received a new thrust with emphasis on VLSI design using non­ ROM based designs as well as ROM based designs as evidenced by the increased publications in this area. The main advantage in using RNS is that several small word-length Processors are used to perform operations such as addition, multiplication and accumulation, subtraction, thus needing less instruction execution time than that needed in conventional 16 bitl32 bit DSPs. However, the disadvantages of RNS have b. een the difficulty of detection of overflow, sign detection, comparison of two numbers, scaling, and division by arbitrary number, RNS to Binary conversion and Binary to RNS conversion. These operations, unfortunately, are computationally intensive and are time consuming.

Over the past few years, the demand for high speed Digital Signal Proces­ sing (DSP) has increased dramatically. New applications in real-time image processing, satellite communications, radar signal processing, pattern recogni­ tion, and real-time signal detection and estimation require major improvements at several levels; algorithmic, architectural, and implementation. These perfor­ mance requirements can be achieved by employing parallel processing at all levels. Very Large Scale Integration (VLSI) technology supports and provides a good avenue for parallelism. Parallelism offers efficient sohitions to several problems which can arise in VLSI DSP architectures such as: 1. Intermediate data communication and routing: several DSP algorithms, such as FFT, involve excessive data routing and reordering. Parallelism is an efficient mechanism to minimize the silicon cost and speed up the pro­ cessing time of the intermediate middle stages. 2. Complex DSP applications: the required computation is almost doubled. Parallelism will allow two similar channels processing at the same time.

This informative text/reference presents a detailed review of the state of the art in fog computing paradigm. In particular, the book examines a broad range of important cooperative and distributed computation algorithms, along with their design objectives and technical challenges.

The volume includes papers presented at the International KES Conference on Human Centred Intelligent Systems 2023 (KES HCIS 2023), held in Rome, Italy on June 14–16, 2023. This book highlights new trends and challenges in intelligent systems, which play an important part in the digital transformation of many areas of science and practice. It includes papers offering a deeper understanding of the human-centred perspective on artificial intelligence, of intelligent value co-creation, ethics, value-oriented digital models, transparency, and intelligent digital architectures and engineering to support digital services and intelligent systems, the transformation of structures in digital businesses and intelligent systems based on human practices, as well as the study of interaction and the co-adaptation of humans and systems.

Many modern computer systems, including homogeneous and heterogeneous architectures, support shared memory in hardware. In a shared memory system, each of the processor cores may read and write to a single shared address space. For a shared memory machine, the memory consistency model defines the architecturally visible behavior of its memory system. Consistency definitions provide rules about loads and stores (or memory reads and writes) and how they act upon memory. As part of supporting a memory consistency model, many machines also provide cache coherence protocols that ensure that multiple cached copies of data are kept up-to-date. The goal of this primer is to provide readers with a basic understanding of consistency and coherence. This understanding includes both the issues that must be solved as well as a variety of solutions. We present both high-level concepts as well as specific, concrete examples from real-world systems.

This book is dedicated to the issues of security, trust and privacy models, and architectures in IoT environments. The authors aim to capture the latest research and contributions from academy, industry, and other stakeholders on new security models, architectures, protocols, and standards for ensuring security, privacy, and trustworthiness to IoT systems. The authors discuss the convergence of IoT, software agents, and edge computing to introduce social features into IoT systems, combining trustworthiness and reputation information collected by agents at the edge with security and privacy mechanisms. They also cover experimental and simulated campaigns that evaluate strategies to improve the security and privacy of the IoT world, and at the same time the ability to prevent and deter deceptive behaviors. The book is relevant for researchers, professionals, academics, and students.